A semiconductor integrated circuit chip is typically fabricated with a back-end-of-line (BEOL) interconnect structure, which comprises multiple levels of metal lines and inter-level metal vias, to connect various integrated circuit components and devices that are fabricated as part of a front-end-of-line (FEOL) layer of the semiconductor integrated circuit chip. Current state of the art BEOL process technologies typically use copper to form BEOL interconnect structures, as copper has low resistance, which results in interconnect structures with improved conduction and higher device performance. As copper interconnect structures are scaled down in size, however, resistivity of the copper interconnect structures increases exponentially, which is undesirable.